軟件:Quartus
語言:VHDL
代碼功能:
正弦波發(fā)生器:
使用quartus設(shè)計(jì),VHDL語言設(shè)計(jì)正弦波發(fā)生器;
內(nèi)部存儲正弦波的ROM表,通過仿真波形可以觀察到正弦波。
FPGA代碼Verilog/VHDL代碼資源下載:www.hdlcode.com
演示視頻:
設(shè)計(jì)文檔:
1. 工程文件
2. 程序文件
ROM IP核
3. 程序編譯
4. RTL圖
5. Testbench
6. 仿真圖
部分代碼展示:
LIBRARY?ieee; ???USE?ieee.std_logic_1164.all; USE?ieee.std_logic_unsigned.all; --DDS ENTITY?DDS_top?IS ???PORT?( ??????clk_in??????:?IN?STD_LOGIC;--時(shí)鐘 wave?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--輸出波形 ???); END?DDS_top; ARCHITECTURE?behave?OF?DDS_top?IS --例化模塊 ??? --相位累加器模塊 ???COMPONENT?Frequency_ctrl?IS ??????PORT?( ?????????clk_in??????:?IN?STD_LOGIC; ?????????addra????????:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0) ??????); ???END?COMPONENT; --ROM表 COMPONENT?sin_ROM?IS PORT ( address:?IN?STD_LOGIC_VECTOR?(6?DOWNTO?0); clock:?IN?STD_LOGIC; q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0) ); END?COMPONENT; ??? ???SIGNAL?addra?:?STD_LOGIC_VECTOR(6?DOWNTO?0); BEGIN ???--sin波ROM,存儲波形數(shù)據(jù) ???i_sin_ROM?:?sin_ROM ??????PORT?MAP?( ?????????clock???=>?clk_in,--時(shí)鐘 ?????????address??=>?addra,--ROM地址 ?????????q??=>?wave--輸出波形 ??????);? ??? ???--相位累加器 ???i_Frequency_ctrl?:?Frequency_ctrl ??????PORT?MAP?( ?????????clk_in????=>?clk_in,--時(shí)鐘 ?????????addra??????=>?addra--輸出地址 ??????); ??? END?behave;
點(diǎn)擊鏈接獲取代碼文件:http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=404
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